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tps51461 www.ti.com slusad9 ? december 2010 3.3-v/5-v input, 6-a, d-cap+ ? mode synchronous step-down integrated fets converter with 2-bit vid check for samples: tps51461 1 features description 2 ? integrated fets converter w/ti proprietary the tps51461 is a fully integrated synchronous buck d-cap+ ? mode architecture regulator employing d-cap+ ? . it is used for up to 5-v step-down where system size is at its premium, ? 6-a maximum output current performance and optimized bom are must-haves. ? minimum external parts count this device fully supports intel system agent ? support all mlcc output capacitor and applications with integrated 2-bit vid function. sp/poscap the tps51461 also features two switching frequency ? auto skip mode settings (700 khz and 1 mhz), skip mode, pre-bias ? selectable 700-khz and 1-mhz frequency startup, programmable external capacitor soft-start ? small 4 4, 24-pin, qfn package time/voltage transition time, output discharge, internal vbst switch, 2-v reference ( 1%), power good and applications enable. ? low-voltage applications stepping down from the tps51461 is available in a 4 mm 4 mm, 5-v or 3.3-v rail 24-pin, qfn package (green rohs compliant and pb ? notebook/desktop computers free) and is specified from 0 c to 85 c. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 d-cap+ is a trademark of texas instruments. production data information is current as of publication date. copyright ? 2010, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. tps51461 vin vin sw sw vin pgnd pgnd pgnd sw sw sw bst en mode vout comp slew vref gnd vid0 vid1 pgood v5drv v5filt 19 20 21 22 23 24 1 2 3 4 5 6 12 11 10 9 8 7 18 17 16 15 14 13 vccsa vccsasns udg-10183 enable vin vid0 vid1 +5v pgood
tps51461 slusad9 ? december 2010 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. ordering information (1) minimum t a package (2) ordering number pins output supply eco plan quantity TPS51461RGER 24 tape and reel 3000 green (rohs and plastic qfn 0 c to 85 c no pb/br) (rge) tps51461rget 24 mini reel 250 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or visit the ti website at www.ti.com . (2) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package . thermal information tps51461 thermal metric (1) units rge (24) pin q ja junction-to-ambient thermal resistance 33.6 q jctop junction-to-case (top) thermal resistance 45.0 q jb junction-to-board thermal resistance 10.8 c/w y jt junction-to-top characterization parameter 0.2 y jb junction-to-board characterization parameter 10.4 q jcbot junction-to-case (bottom) thermal resistance 3.8 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) value unit min max vin, en, mode ? 0.3 7.0 v5drv, v5filt, vbst (with respect to sw) ? 0.3 5.5 input voltage range vbst ? 0.3 12.5 v vid0, vid1 ? 0.3 3.6 vout ? 1.0 3.6 sw ? 2.0 7.0 sw (transient 20 ns and e=5 j) ? 3.0 output voltage range comp, slew, vref ? 0.3 3.6 v pgnd ? 0.3 0.3 pgood ? 0.3 7.0 human body model (hbm) 2000 electrostatic discharge v charged device model (cdm) 500 storage temperature t stg ? 55 150 ? c junction temperature t j 0 150 ? c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 ? c (1) stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461
tps51461 www.ti.com slusad9 ? december 2010 recommended operating conditions value unit min typ max vin, en, mode ? 0.1 6.5 v5drv, v5filt, vbst(with respect to sw) ? 0.1 5.25 input voltage range vbst ? 0.1 11.75 v vid0, vid1 ? 0.1 3.5 vout ? 0.8 2.0 sw ? 1.8 6.5 comp, slew, vref ? 0.1 3.5 output voltage range v pgood ? 0.1 6.5 pgnd ? 0.1 0.1 ambient temperature range, t a 0 85 c copyright ? 2010, texas instruments incorporated submit documentation feedback 3 product folder link(s): tps51461
tps51461 slusad9 ? december 2010 www.ti.com electrical characteristics over recommended free-air temperature range, v vin = 5.0 v, v v5drv = v v5filt = 5 v, mode = open, pgnd = gnd (unless otherwise noted) parameter conditions min typ max unit supply: voltage, currents and 5 v uvlo i vinsd vin shutdown current en = ' lo ' 0.02 5 a v 5vin 5vin supply voltage v5drv and v5filt voltage range 4.50 5.00 5.25 v i 5vin 5vin supply current en = ? hi ? , v5drv + v5filt supply current 1.1 2 ma i 5vinsd 5vin shutdown current en = ? lo ? , v5drv + v5filt shutdown current 10 50 a v v5uvlo v5filt uvlo ramp up; en = ' hi ' 4.2 4.3 4.5 v v v5uvhys v5filt uvlo hysteresis falling hysteresis 440 mv v vrefuvlo ref uvlo (1) rising edge of vref, en = ' hi ' 1.8 v v vrefuvhys ref uvlo hysteresis (1) 100 mv v por5vfilt reset ovp latch is reset by v5filt falling below the reset threshold 1.5 2.3 3.1 v voltage feedback loop: vref, vout, and voltage gm amplifier v outtol vout accuracy v vout = 0.8v, no droop ? 1.5% 0% 1.5% v vref vref i vref = 0 a, t a = 25 c 2.01 v i vrefsnk vref sink current vref within tolerance, v vref = 2.05 v 2.5 ma g m transconductance 1 ms v dm differential mode input voltage 0 80 mv i compsrc comp pin maximum sourcing current v comp = 2 v ? 80 a v offset input offset voltage t a = 25 c ? 3 0 3 mv r dsch output voltage discharge resistance 42 f ? 3dbvl ? 3db frequency (1) 6 mhz current sense: current sense amplifier, over current and zero crossing gain from the current of the low-side fet to pwm comparator a csint internal current sense gain 48 53 57 mv/a when pwm = " off " i ocl positive overcurrent limit (valley) 6 7.5 a i ocl(neg) negative overcurrent limit (valley) ? 6.5 ? 5.0 a v zxoff zero crossing comp internal offset 0 mv drivers: boot strap switch r dsonbst internal bst switch on-resistance i vbst = 10 ma, t a = 25 c 5 10 i bstlk internal bst switch leakage current v vbst = 14 v, v sw = 7 v, t a = 25 c 1 a (1) ensured by design, not production tested. 4 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461
tps51461 www.ti.com slusad9 ? december 2010 electrical characteristics (continued) over recommended free-air temperature range, v vin = 5.0 v, v v5drv = v v5filt = 5 v, mode = open, pgnd = gnd (unless otherwise noted) parameter conditions min typ max unit protection: ovp, uvp, pgood, and thermal shutdown pgood deassert to lower v pgdll measured at the vout pin w/r/t v slew 82% 84% 86% (pgood low) v pghyshl pgood high hysteresis 8% pgood de-assert to higher v pgdlh measured at the vout pin w/r/t v slew 114% 116% 118% (pgood low) v pghyshh pgood high hysteresis -8% minimum vin voltage for valid measured at the vin pin with a 2-ma sink current on pgood v inminpg 1.0 1.3 1.5 v pgood pin v ovp ovp threshold measured at the vout pin w/r/t v slew 118% 120% 122% measured at the vout pin w/r/t v slew , device latches off, v uvp uvp threshold 66% 68% 70% begins soft-stop th sd thermal shutdown (2) latch off controller, attempt soft-stop. 130 c th sd(hys) thermal shutdown hysteresis (2) controller re-starts after temperature has dropped 10 c timers: on-time, minimum off time, ss, and i/o timings v vin = 5 v, v vout = 0.8 v, f sw = 667 khz, fixed vid mode 240 ns t oneshotc pwm one-shot (2) v vin = 5 v, v vout = 0.8 v, f sw = 1 mhz, fixed vid mode 160 ns v vin = 5 v, v vout = 0.8 v, f sw = 1 mhz, drvl on, t min(off) minimum off time 357 ns sw = pgnd, v vout < v slew pgood startup delay time (excl. delay starts from vout = vid code 00 and excludes slew t pgddly 3 ms slew ramp up time) ramp up time t pgdpdlyh pgood high propagation delay time 50 mv over drive, rising edge 0.8 1 1.2 ms t pgdpdlyl pgood low propagation delay time 50 mv over drive, falling edge 10 s t ovpdly ovp delay time time from the vout pin out of +20% of v slew to ovp fault 0.2 s undervoltage fault enable delay (excl. time from (vout = vid code 00) going high to undervoltage t uvdlyen 3 ms slew ramp up time) fault is ready t uvpdly uvp delay time time from the vout pin out of ? 30% of v slew to uvp fault 8.5 s i slew soft-start and voltage transition c ss = 10 nf assuming voltage slew rate of 1 mv/ s 9 10 11 a logic pins: i/o voltage and current v pgdpd pgood pull down voltage pgood low impedance, i sink = 4 ma, v vin = v v5filt = 4.5 v 0.3 v i pgdlkg pgood leakage current pgood high impedance, forced to 5.5 v ? 1 0 1 a v enh en logic high en, vccp logic 0.8 v v enl en logic low en, vccp logic 0.3 v i en en input current 1 a v vidh vid logic high vid0, vid1 0.8 v v vidl vid logic low vid0, vid1 0.3 v i vid vid input current 1 a mode 1 0.08 0.13 0.18 mode 3 0.37 0.42 0.47 v modeth mode threshold voltage (3) mode 4 0.55 0.60 0.65 v mode 5 0.83 0.88 0.93 mode 7 1.75 1.80 1.85 i mode mode current 15 a r pd vid pull-down resistance 10 k (2) ensured by design, not production tested. (3) see table 3 for descriptions of mode parameters. copyright ? 2010, texas instruments incorporated submit documentation feedback 5 product folder link(s): tps51461
tps51461 slusad9 ? december 2010 www.ti.com rge package pin functions pin i/o description no. name 19 20 pgnd i power ground. source terminal of the rectifying low-side power fet. positive input for current sensing. 21 22 23 vin i power supply input pin. drain terminal of the switching high-side power fet. 24 1 gnd ? signal ground. 2 vref o 2.0-v reference output. connect a 0.22- f ceramic capacitor to gnd. 3 comp o connect series r/c or r between this pin and vref for loop compensation. 4 slew i/o program the startup and voltage transition time using an external capacitor via 10- a current source. 5 vout i output voltage monitor input pin. 6 mode i allows selection of switching frequencies and output voltage. (see table 3 ) 7 8 9 sw i/o switching node output. connect to the external inductor. also serve as current-sensing negative input. 10 11 12 power supply for internal high-side gate driver. connect a 0.1- f bootstrap capacitor between this pin and bst i the sw pin. 13 en i enable of the smps. 14 vid0 i 2-bit vid input. 15 vid1 16 pgood o power good output. connect pull-up resistor. 17 v5filt i 5-v power supply for analog circuits. 18 v5drv i 5-v power supply for the gate driver. 6 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461 tps51461rge vin vin sw sw vin pgnd pgnd pgnd sw sw sw bst en mode vout comp slew vref gnd vid0 vid1 pgood v5drv v5filt 23 4 5 6 7 8 9 10 11 1 12 13 14 15 16 17 18 24 23 22 21 20 19 thermal pad
tps51461 www.ti.com slusad9 ? december 2010 block diagram table 1. intel sa vid vid 0 vid 1 vccsa 0 0 0.9 v 0 1 0.80v (1) mode = open 0 1 0.85v (1) mode = 33 k 1 0 0.725 v 1 1 0.675 v (1) 0.80v for 2011 sv processor and 0.85v for 2011 lv/ulv processor copyright ? 2010, texas instruments incorporated submit documentation feedback 7 product folder link(s): tps51461 19 7 pgnd sw tps51461 oc zc xcon 12 bst 18 v5drv pwm 5 en 16 pgood control logic udg-10184 + + v refin +20% + + 13 vout + vin t on one- shot uv ov v refin C32% 4 slew + 8 r 3 comp r 1 gnd 2 vref on-time and ll selection 15 m a 6 mode v refin +8/16 % v refin C8/16 % + + discharge uvp ovp 17 v5filt bandgap sense + 00 01 10 11 + vs cs 14 vid0 15 vid1 10 m a sw pgnd 22 23 24 vin vin 8 sw 9 sw 10 sw 11 sw 20 pgnd 21 pgnd vcs
tps51461 slusad9 ? december 2010 www.ti.com application schematic with tps51461 figure 1. application schematic using non-droop configuration, and recommended reference design for intel sa application 8 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461 tps51461 vin vin sw sw vin pgnd pgnd pgnd sw sw sw bst en mode vout comp slew vref gnd vid0 vid1 pgood v5drv v5filt 19 20 21 22 23 24 1 2 3 4 5 6 12 11 10 9 8 7 18 17 16 15 14 13 0.1 m f dnp l 0.42 m h 22 m f 100 w dnp dnp vccsa vccsasns udg-10186 0.22 m f 5 k w 10 nf enable vid0 vid1 +5v 0 w 1 m f 2 k w 100 k w pgood 0.1 m f 10 m f 10 m f vin 22 m f 22 m f 22 m f 22 m f 3.3 nf
tps51461 www.ti.com slusad9 ? december 2010 figure 2. application schematic using droop configuration copyright ? 2010, texas instruments incorporated submit documentation feedback 9 product folder link(s): tps51461 tps51461 vin vin sw sw vin pgnd pgnd pgnd sw sw sw bst en mode vout comp slew vref gnd vid0 vid1 pgood v5drv v5filt 19 20 21 22 23 24 1 2 3 4 5 6 12 11 10 9 8 7 18 17 16 15 14 13 0.1 m f dnp l 0.42 m h 22 m f dnp dnp vccsa vccsasns udg-10185 0.22 m f 10 k w 10 nf enable vid0 vid1 +5v 0 w 1 m f 2 k w 100 k w pgood 0.1 m f 10 m f 10 m f vin 22 m f 22 m f 22 m f 22 m f 22 m f 0 w 22 m f
tps51461 slusad9 ? december 2010 www.ti.com application circuit list of materials recommended parts for key external components for the circuits in figure 1 and figure 2 are listed in table 2 . table 2. key external component recommendations ( figure 1 and figure 2 ) function manufacturer part number output inductor nec-tokin mpcg0740lr42c panasonic ecj2fb0j226m ceramic output capacitors murata grm21br60j226me39l 10 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461
tps51461 www.ti.com slusad9 ? december 2010 application information functional overview the tps51461 is a d-cap+ ? mode adaptive on-time converter. the output voltage is set using a 2-bit dac that outputs a reference voltage in accordance with the code defined in table 1 . vid-on-the-fly transitions are supported with the slew rate controlled by a single capacitor on the slew pin. integrated high-side and low-side fet supports output current to a maximum of 6-adc. the converter automatically runs in discontinuous conduction mode (dcm) to optimize light-load efficiency. two switching frequency selections are provided, (700 khz and 1 mhz) to enable optimization of the power chain for the cost, size and efficiency requirements of the design. in adaptive on-time converters, the controller varies the on-time as a function of input and output voltage to maintain a nearly constant frequency during steady-state conditions. in conventional constant on-time converters, each cycle begins when the output voltage crosses to a fixed reference level. however, in the tps51461, the cycle begins when the current feedback reaches an error voltage level which is the amplified difference between the reference voltage and the feedback voltage. pwm operation referring to figure 3 , in steady state, continuous conduction mode, the converter operates in the following way. starting with the condition that the top fet is off and the bottom fet is on, the current feedback (v cs ) is higher than the error amplifier output (v comp ). v cs falls until it hits v comp , which contains a component of the output ripple voltage. v cs is not directly accessible by measuring signals on pins of tps51461. the pwm comparator senses where the two waveforms cross and triggers the on-time generator. figure 3. d-cap+ ? mode basic waveforms the current feedback is an amplified and filtered version of the voltage between pgnd and sw during low-side fet on-time. the tps51461 also provides a single-ended differential voltage (v out ) feedback to increase the system accuracy and reduce the dependence of circuit performance on layout. copyright ? 2010, texas instruments incorporated submit documentation feedback 11 product folder link(s): tps51461 time ( m s) voltage (v) current feedback t on t v cs v comp udg-10187 v ref
tps51461 slusad9 ? december 2010 www.ti.com pwm frequency and adaptive on time control in general, the on-time (at the sw node) can be estimated by equation 1 . where ? f sw is the frequency selected by the connection of the mode pin (1) the on-time pulse is sent to the top fet. the inductor current and the current feedback rises to peak value. each on pulse is latched to prevent double pulsing. switching frequency settings are shown in table 3 . non-droop configuration the tps51461 can be configured as a non-droop solution. the benefit of a non-droop approach is that load regulation is flat, therefore, in a system where tight dc tolerance is desired, the non-droop approach is recommended. for the intel system agent application, non-droop is recommended as the standard configuration. the non-droop approach can be implemented by connecting a resistor and a capacitor between the comp and the vref pins. the purpose of the type ii compensation is to obtain high dc feedback gain while minimizing the phase delay at unity gain cross over frequency of the converter. the value of the resistor (r c ) can be calculated using the desired unity gain bandwidth of the converter, and the value of the capacitor (c c ) can be calculated by knowing where the zero location is desired. an application tool that calculates these values is available from your local ti field application engineer. figure 4 shows the basic implementation of the non-droop mode using the tps51461. figure 4. non-droop mode basic implementation figure 5 shows the load regulation of the system agent rail using non-droop configuration. figure 6 shows the transient response of tps51461 using non-droop configuration where c out = 4 22 f. the applied step load is from 0 a to 2 a. 12 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461 = out on in sw v 1 t v f + v slew + C r c + pwm comparator r ds(on) g mv = 1 ms driver l out esr c out r out udg-10190 r load 8 k w + C + g mc = 1 ms c c vref
tps51461 www.ti.com slusad9 ? december 2010 figure 5. 0.8-v load regulation (v in = 5 v) figure 6. non-droop configuration transient non-droop configuration response droop configuration the terminology for droop is the same as load line or voltage positioning as defined in the intel cpu v core specification. based on the actual tolerance requirement of the application, load-line set points can be defined to maximize either cost savings (by reducing output capacitors) or power reduction benefits. accurate droop voltage response is provided by the finite gain of the droop amplifier. the equation for droop voltage is shown in equation 2 . where ? low-side on-resistence is used as the current sensing element ? a csint is a constant, which nominally is 53 mv/a. ? i(l) is the dc current of the inductor, or the load current ? r droop is the value of resistor from the comp pin to the vref pin ? g m is the transconductance of the droop amplifier with nominal value of 1 ms (2) (3) therefore, if a 5-m load line to the system agent rail is desired, the calculated r droop is approximately 10 k . equation 2 can be used to easily derive r droop for any load line slope/droop design target. copyright ? 2010, texas instruments incorporated submit documentation feedback 13 product folder link(s): tps51461 = csint droop droop m a i(l) v r g 0.73 0.75 0.77 0.79 0.81 0.83 0.85 0.87 0 1 2 3 4 5 6 output current (a) output voltage (v) mode 3mode 4 mode 7 mode 8 v in = 5 v = = \ = droop csint csint load _ line droop droop m load _ line m v a a r r i(l) r g r g
tps51461 slusad9 ? december 2010 www.ti.com figure 7 shows the basic implementation of the droop mode using the tps51461. figure 7. droop mode basic implementation the droop (voltage positioning) method was originally recommended to reduce the number of external output capacitors required. the effective transient voltage range is increased because of the active voltage positioning (see figure 8 ). figure 8. droop vs non-droop in transient voltage window 14 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461 udg-10189 droop i load v out setpoint at 0 a maximum undershoot voltage =(5%C1%) x 1 = 4% x v out lead insertion lead release non- droop maximum transient voltage = (5%C1%) x 2 = 8% x v out v out setpoint at 6 a v out setpoint at 0 a maximum overshoot voltage =(5%C1%) x 1 = 4% x v out + v slew + C r droop + pwm comparator r ds(on) g mv = 1 ms driver l out esr c out r out udg-10188 r load 8 k w + C + g mc = 1 ms vref
tps51461 www.ti.com slusad9 ? december 2010 consider an example of 0.8 v 5%. if no droop is permitted, the allowable transient overshoot can be at a maximum of +4%; the allowed transient undershoot can only be at minimum of ? 4% (given a dc tolerance of 1%). therefore, the overshoot and undershoot window is only 32 mv. if the droop method is applied, this overshoot and undershoot window could be potentially doubled from 32 mv to 64 mv, given the same load step and release. in applications where the dc and the ac tolerances are not separated, which means there is not a strict dc tolerance requirement, the droop method can be used. table 3. mode parameter table compensation switching vid1 = 1 technology mode mode vref (v) frequency vid0 = 0 connection non- (f sw ) (v) droop droop 1 gnd x 2.05 1 mhz 0.80 3 22 k x x 2.00 700 khz 0.80 4 33 k x x 2.00 1 mhz 0.85 5 47 k x 2.05 1 mhz 0.85 7 100 k x x 2.00 700 khz 0.85 8 open x x 2.00 1 mhz 0.80 figure 9 shows the load regulation of the 0.8-v rail using an r droop value of 10 k . figure 10 shows the transient response of the tps51461 using droop configuration and c out = 4 22 f. the applied step load is from 0 a to 2 a. figure 9. 0.8-v load regulation (v in = 3.3 v) figure 10. droop configuration transient response copyright ? 2010, texas instruments incorporated submit documentation feedback 15 product folder link(s): tps51461 0.75 0.76 0.77 0.78 0.79 0.80 0.81 0.82 0.83 0.84 0 1 2 3 4 5 6 output current (a) output voltage (v) v in = 3.3 v
tps51461 slusad9 ? december 2010 www.ti.com light load power saving features the tps51461 has an automatic pulse-skipping mode to provide excellent efficiency over a wide load range. the converter senses inductor current and prevents negative flow by shutting off the low-side gate driver. this saves power by eliminating re-circulation of the inductor current. further, when the bottom fet shuts off, the converter enters discontinuous mode, and the switching frequency decreases, thus reducing switching losses as well. voltage slewing the tps51461 ramps the slew voltage up and down to perform the output voltage transitioning. the timing is independent of switching frequency, as well as output resistive and capacitive loading. it is set by a capacitor from slew pin to gnd, called c slew , together with an internal current source of 10 a. the slew rate is used to set the startup and voltage transition rate. (4) where ? i slew = 10 a (nom) ? sr is the target output voltage slew rate, per intel specification between 0.5 mv/ s and 10 mv/ s (5) for the current reference design, an sr of 1 mv/ s is targeted. the c slew is calculated to be 10 nf. the slower slew rate is desired to minimize large inductor current perturbation during startup and voltage transitioning thus reducing the possibility of acoustic noise. after the power up, when vid1 is transitioning from 0 to 1, tps51461 follows the slew voltage entering the forced pwm mode to actively discharge the output voltage from 0.9 v to 0.8 v. the actual output voltage slew rate is approximately the same as the set slew rate while the bandwidth of the converter supports it and there is no overcurrent triggered by additional charging current flowing into the output capacitors. after slew transition is completed, pwm mode is maintained for 64 s (16 clock cycles when the frequency is 1 mhz) to ensure voltage regulation. protection features the tps51461 offers many features to protect the converter power chain as well as the system electronics. 5-v undervoltage protection (uvlo) the tps51461 continuously monitors the voltage on the v5filt pin to ensure that the voltage level is high enough to bias the device properly and to provide sufficient gate drive potential to maintain high efficiency. the converter starts with approximately 4.3 v and has a nominal of 440 mv of hysteresis. if the 5-v uvlo limit is reached, the converter transitions the phase node into a 3-state function. and the converter remains in the off state until the device is reset by cycling 5 v until the 5-v por is reached (2.3-v nominal). the power input does not have an uvlo function power good signals the tps51461 has one open-drain power good (pgood) pin. during startup, there is a 3 ms power good delay starting from the output voltage reaching the regulation point (excluding soft-start ramp-up time). and there is also a 1 ms power good high propagation delay. the pgood pin de-asserts as soon as the en pin is pulled low or an undervoltage condition on v5filt is detected. the pgood signal is blanked during vid voltage transitions to prevent false triggering during voltage slewing. 16 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461 = slew ss slew c 0.9 v t i = slew slew i c sr
tps51461 www.ti.com slusad9 ? december 2010 output overvoltage protection (ovp) in addition to the power good function described above, the tps51461 has additional ovp and uvp thresholds and protection circuits. an ovp condition is detected when the output voltage is approximately 120% v slew . in this case, the converter de-asserts the pgood signals and performs the overvoltage protection function. the converter remains in this state until the device is reset by cycling 5 v until the 5-v por threshold (2.3 v nominal) is reached. output undervoltage protection (uvp) output undervoltage protection works in conjunction with the current protection described in the overcurrent protection and overcurrent limit sections. if the output voltage drops below 70% of v slew , after an 8- s delay, the device latches off. undervoltage protection can be reset only by en or a 5-v por. overcurrent protection both positive and negative overcurrent protection are provided in the tps51461: ? overcurrent limit (ocl) ? negative ocl (level same as positive ocl) overcurrent limit if the sensed current value is above the ocl setting, the converter delays the next on pulse until the current drops below the ocl limit. current limiting occurs on a pulse-by-pulse basis. the tps51461 uses a valley current limiting scheme where the dc ocl trip point is the ocl limit plus half of the inductor ripple current. the minimum valley ocl is 6 a over process and temperature. during the overcurrent protection event, the output voltage likely droops until the uvp limit is reached. then, the converter de-asserts the pgood pin, and then latches off after an 8- s delay. the converter remains in this state until the device is reset by en or a 5vfilt por. (6) negative ocl the negative ocl circuit acts when the converter is sinking current from the output capacitor(s). the converter continues to act in a valley mode, the absolute value of the negative ocl set point is typically -6.5 a. thermal protection thermal shutdown the tps51461 has an internal temperature sensor. when the temperature reaches a nominal 130 c, the device shuts down until the temperature cools by approximately 10 c. then the converter restarts. copyright ? 2010, texas instruments incorporated submit documentation feedback 17 product folder link(s): tps51461 ( ) ( ) - = + p p ocl dc ocl valley 1 i i i 2
tps51461 slusad9 ? december 2010 www.ti.com startup and vid transition timing diagrams figure 11. fixed vid/fixed step startup and vid toggle timing diagram for 2011 intel platform for figure 11 : (1) includes vcca, vccaxg, and vddq power rails. (2) processor reset: vid transition must be completed by this time. (3) 1-k pull-down resistor required. 18 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461 vccp 0.95 v 1.05-v rail 260 m s en internal enable vid1 (3) vid0 (3) slew (1 mv/ m s) vout vccsa_pgood uncore_pwrgd (1) 900 m s 4 ms 2.5 ms reset time (2) udg-10191
tps51461 www.ti.com slusad9 ? december 2010 figure 12. fixed vid/fixed step startup and vid toggle timing diagram for 2012 intel platform for figure 12 : (1) includes vcca, vccaxg, and vddq power rails. (2) processor reset: vid transition must be completed by this time. (3) 1-k pull-down resistor required. copyright ? 2010, texas instruments incorporated submit documentation feedback 19 product folder link(s): tps51461 vccp 0.95 v 1.05-v rail 260 m s en internal enable vid1 (3) vid0 (3) slew (1 mv/ m s) vout vccsa_pgood uncore_pwrgd (1) 900 m s 4 ms 2.5 ms reset time (2) udg-10192 100 m s
tps51461 slusad9 ? december 2010 www.ti.com typical characteristics figure 13. efficiency vs output current figure 14. efficiency vs output current figure 15. power loss figure 16. power loss figure 17. bode plot (non-droop mode) v in = 5 v, figure 18. bode plot (droop mode), v in = 5 v, v out = 0.8 v, i load = 5 a v out = 0.8 v, i load = 5 a 20 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461 60 110 160 210 260 310 360 10 -40 -30 -20 -10 30 40 50 -40 -50 0 10 20 frequency (hz) gain phase 25c -10c 85c 1000 10 k 100 k 1 m 10 m gain (db) phase () 60 100 150 200 250 300 350 400 50 0 -30 -20 -10 30 40 50 -40 -50 0 10 20 frequency (hz) gain phase 1000 10 k 100 k 1 m 10 m gain (db) phase () 25c -10c 85c 40 45 50 55 60 65 70 75 80 85 90 0.01 0.1 1 10 output current (a) efficiency (%) mode 1mode 3 mode 4 mode 7 mode 8 t a = 25c v in = 3.3 v 0.00 0.25 0.50 0.75 1.00 1.25 0.1 1 10 output current (a) power loss (w) mode 1mode 3 mode 4 mode 7 mode 8 t a = 25c v in = 5 v 0.00 0.25 0.50 0.75 1.00 1.25 0.1 1 10 output current (a) power loss (w) mode 1mode 3 mode 4 mode 7 mode 8 t a = 25c v in = 3.3 v 40 45 50 55 60 65 70 75 80 85 90 0.01 0.1 1 10 output current (a) efficiency (%) mode 1mode 3 mode 4 mode 7 mode 8 t a = 25c v in = 5 v
tps51461 www.ti.com slusad9 ? december 2010 typical characteristics (continued) figure 19. mode 8 non-droop, 0 a figure 20. mode 8 non-droop, 3 a figure 21. mode 8 droop, 0 a figure 22. mode 8 droop, 3 a figure 23. mode 4 non-droop 0 a figure 24. mode 4 non-droop 3 a copyright ? 2010, texas instruments incorporated submit documentation feedback 21 product folder link(s): tps51461
tps51461 slusad9 ? december 2010 www.ti.com typical characteristics (continued) figure 25. mode 4 droop 0 a figure 26. mode 4 droop 3 a 22 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461
tps51461 www.ti.com slusad9 ? december 2010 design procedure the simplified design procedure is done for a non-droop application using the tps51461 converter. step one determine the specifications. the system agent rail requirements provide the following key parameters: 1. v 00 = 0.90 v 2. v 10 = 0.80 v 3. i cc(max) = 6 a 4. i dyn(max) = 2 a 5. i cc(tdc) = 3 a step two determine system parameters. the input voltage range and operating frequency are of primary interest. for example: 1. v in = 5 v 2. f sw = 1 mhz step three determine inductor value and choose inductor. smaller values of inductor have better transient performance but higher ripple and lower efficiency. higher values have the opposite characteristics. it is common practice to limit the ripple current to 25% to 50% of the maximum current. in this case, use 25%: (7) at f sw = 1 mhz, with a 5-v input and a 0.80-v output: (8) for this application, a 0.42- h, 1.55-m inductor from nec-tokin with part number mpcg0740lr42c is chosen. step four set the output voltage. the output voltage is determined by the vid settings. the actual voltage set point for each vid setting is listed in table 1 . no external resistor dividers are needed for this design. step five calculate c slew . vid pin transition and soft-start time is determined by c slew and 10 a of internal current source. (9) the slower slew rate is desired to minimize large inductor current perturbation during startup and voltage transition, thus reducing the possibility of acoustic noise. copyright ? 2010, texas instruments incorporated submit documentation feedback 23 product folder link(s): tps51461 m = = = m slew slew dac i 10 a c 10nf 1 mv sr s ( ) ( ) ( ) ( ) - - ? ? ? ? - - ? ? ? ? ? ? = = = = m 10 in 10 sw in p p p p v 0.8 v v 5 0.8 f v 1 5 v dt l 0.45 h i i 1.5 a - = = p p i 6 a 0.25 1.5 a
tps51461 slusad9 ? december 2010 www.ti.com given the c slew , use equation 10 to calculate the soft start time. (10) step six calculate ocl. the dc ocl level of tps51461 design is determined by equation 11 , (11) the minimum valley ocl is 6 a over process and temperature, and i p-p = 1.5 a, the minimum dc ocl is calculated to be 6.75a. step seven determine the output capacitance. to determine cout based on transient and stability requirement, first calculate the the minimum output capacitance for a given transient. equation 13 and equation 12 can be used to estimate the amount of capacitance needed for a given dynamic load step/release. please note that there are other factors that may impact the amount of output capacitance for a specific design, such as ripple and stability. equation 13 and equation 12 are used only to estimate the transient requirement, the result should be used in conjunction with other factors of the design to determine the necessary output capacitance for the application. (12) (13) equation 12 and equation 13 calculate the minimum c out for meeting the transient requirement, which is 72.9 f assuming the following: ? 3% voltage allowance for load step and release ? mlcc capacitance derating of 60% due to dc and ac bias effect in this reference design, 4, 22- f capacitors are used in order to provide this amount of capacitance. 24 submit documentation feedback copyright ? 2010, texas instruments incorporated product folder link(s): tps51461 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ? ? ? d + ? ? = ? ? ? ? - ? ? d - ? ? ? ? 2 vout sw load max min off in min out min_ under vout in min sw vout load insert min off in min v t l i t v c v v 2 v t t v v = = = m m slew ss slew c 0.9 v 10nf 0.9 v t 900 s i 10 a ( ) ( ) - = + = + = p p ocl dc ocl valley 1 1 i i i 6 a 1.5 a 6.75 a 2 2 ( ) ( ) ( ) ( ) d = d 2 out load max out min_ over vout load release l i c 2 v v
tps51461 www.ti.com slusad9 ? december 2010 step eight determine the stability based on the output capacitance c out . in order to achieve stable operation. the 0-db frequency, f 0 should be kept less than 1/5 of the switching frequency (1 mhz). (see figure 4 ) where ? r s = r ds(on) g mc r load (14) . (15) using 4, 22- f capacitors, the compensation resistance, r c can be calculated to be approximately 5 k . the purpose of the comparator capacitor (c c ) is to reduce the dc component to obtain high dc feedback gain. however, as it causes phase delay, another zero to cancel this effect at f 0 is needed. this zero can be determined by values of c c and the compensation resistor, r c . (16) and since r c has previously been derived, the value of c c is calculated to be 2.2 nf. in order to further boost phase margin, a value of 3.3-nf is chosen for this reference design. step nine select decoupling and peripheral components. for tps51461 peripheral capacitors use the following minimum values of ceramic capacitance. x5r or better temperature coefficient is recommended. tighter tolerances and higher voltage ratings are always appropriate. ? v5drv decoupling 2.2 f, 10 v ? v5filt decoupling 1 f, 10 v ? vref decoupling 0.22 f to 1 f, 4 v ? bootstrap capacitors 0.1 f, 10 v ? pull-up resistors on pgood, 100 k layout considerations good layout is essential for stable power supply operation. follow these guidelines for an efficient pcb layout. ? connect pgnd pins (or at least one of the pins) to the thermal pad underneath the device. also connect gnd pin to the thermal pad underneath the device. use four vias to connect the thermal pad to internal ground planes. ? place vin, v5drv, v5filt and 2vref decoupling capacitors as close to the device as possible. ? use wide traces for the vin, vout, pgnd and sw pins. these nodes carry high current and also serve as heat sinks. ? place feedback and compensation components as close to the device as possible. ? keep analog signals (slew, comp) away from noisy signals (sw, vbst). copyright ? 2010, texas instruments incorporated submit documentation feedback 25 product folder link(s): tps51461 = = p c m 0 out s r g 1 f 150khz 2 c r = p = 0 z c c f 1 f 2 r c 10 p w p m = = ? w 0 s out c m f r 2 c 150khz 53m 2 88 f r 5k g 1ms
package option addendum www.ti.com 20-dec-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) TPS51461RGER active vqfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples tps51461rget active vqfn rge 24 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year purchase samples (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS51461RGER vqfn rge 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 tps51461rget vqfn rge 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 q2 package materials information www.ti.com 18-dec-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS51461RGER vqfn rge 24 3000 346.0 346.0 29.0 tps51461rget vqfn rge 24 250 190.5 212.7 31.8 package materials information www.ti.com 18-dec-2010 pack materials-page 2

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